With reference to the drawing, an explanation will be made on a conventional operational amplifier. As shown in FIG. 19, the conventional operational amplifier comprises: a differential input stage 1 (1901) which receives differential input signals at a differential input terminal (IN191) and a differential input terminal (IN192); a differential input stage 2 (1902) which receives differential input signals at a differential input terminal (IN193) and a differential input terminal (IN194); a constant current source 1 (CCS1) (1911) which is coupled between the differential input stage 1 (1901) and the ground; a constant current source 2 (CCS2) (1922) which is coupled between the differential input stage 2 (1902) and a power source; an output terminal (OUT) (1903) for outputting an output signal of the operational amplifier; P-channel FET M1 (1904) whose source electrode is coupled with a power source VCC (1931), whose drain electrode is coupled with the output terminal (1903), and which sources an output current to a load (not shown in the drawing) coupled via the output terminal (1903); and N-channel FET M2 (1905) whose source electrode is coupled with the ground power source VSS (1932), whose drain electrode is coupled with the output terminal (1903), and which sinks an output current from the load (not shown in the drawing) coupled via the output terminal (1903).
The conventional operational amplifier shown in FIG. 19 further comprises: an N channel FET M3 (1907) whose drain electrode is coupled with the differential input stage 1 (1901), whose gate electrode is coupled with the output terminal (1903), and which controls the differential input stage 1 (1901) in response to the output signal level of the output terminal (1903); an N channel FET M4 (1908) whose drain electrode is coupled with the source electrode of the N channel FET M3 (1907), whose gate electrode receives a first control signal of a driver stage circuit (1935), and whose source electrode is coupled with the ground power source VSS (1933); a P-channel FET M5 (1909) whose source electrode is coupled with the power source VCC (1934), whose gate electrode receives a second control signal of the driver stage circuit (1935), and which, in response to an output potential level of the output terminal (1903), controls the differential input stage 2 (1902); and a P-channel FET M6 (1910) whose drain electrode is coupled with the differential input stage 2 (1902), whose source electrode is coupled with the drain electrode of the P-channel FET M5 (1909), and whose gate electrode is coupled with the output terminal (1903).
Also, the differential input stage 1 (1901) comprises a differential transistor pair of well known technology and a current mirror circuit of well known technology, and the differential input stage 2 (1902) comprises a differential transistor pair of well known technology and a load circuit of well known technology.
That is, the differential input stage 1 (1901) comprises a first differential transistor pair (MM5, MM6) wherein one gate electrode is coupled with the differential input terminal (IN191) and the other gate electrode is coupled with the differential input terminal (IN192); a first current mirror circuit (MM1, MM2) which is coupled between the output terminal on the negative signal side of the first differential transistor pair (MM5, MM6) and the high potential power supply conductor VCC (1931); and a second current mirror circuit (MM3, MM4) which is coupled between the output terminal on the positive signal side of the first differential transistor pair (MM5, MM6) and the high potential power supply conductor VCC (1931).
Also, the differential input stage 2 (1902) comprises: a second differential transistor pair (MM7, MM8) wherein one gate electrode is coupled with the differential input terminal (IN193) and the other gate electrode is coupled with the differential input terminal (IN194); and a load circuit (MM9, MM10) which is coupled between the second differential transistor pair (MM7, MM8) and the low potential power supply conductor VSS (1932).
Next, with reference again to FIG. 19, an operation of the conventional operational amplifier will be briefly explained. When, in the conventional operational amplifier, signals are applied to the differential input stage 1 (1901) and the differential input stage 2 (1902) so as to raise the potential of the output terminal (1903), a signal potential at the gate electrode of the P-channel FET M1 (1904) and a signal potential at the gate electrode of the N-channel FET M2 (1905) fall, and these signals are inputted to the gate electrodes of the P-channel FET M5 (1909) and the N-channel FET M4 (1908), respectively.
In this case, to the gate electrode of the P-channel FET M5 (1909), the fallen gate signal of the P-channel FET M1 (1904) is inputted, and a current flowing through the differential input stage 2 (1902) increases, thereby, a high slew rate can be obtained.
On the other hand, in the conventional operational amplifier, when signals are applied to the differential input stage 1 (1901) and the differential input stage 2 (1902) so as to lower the potential of the output terminal (1903), a signal potential at the gate electrode of the P-channel FET M1 (1904) and a signal potential at the gate electrode of the N-channel FET M2 (1905) rise, and these signals are inputted to the gate electrodes of the P-channel FET M5 (1909) and the N-channel FET M4 (1908), respectively. In this case, to the gate electrode of the N-channel FET M4 (1908), the risen gate signal of the N-channel FET M2 (1905) is inputted, and a current flowing through the differential input stage 1 (1901) increases, thereby, a high slew rate can be obtained.
Such operational amplifier is described, for example, in the patent document 1 below.
[Patent Document]
Japanese patent laid-open publication No. 11-088076 (paragraph numbers [0026]-[0035], FIG. 1 and FIG. 2)
However, it is required that an operational amplifier for driving a load has a small power consumption and a high slew rate. To improve the slew rate, various technologies are proposed. For example, a technology in which a slew rate is controlled by using an external signal, and so on are proposed. However, in each of these technologies, a current value is increased even when no change exists in a data signal, or an external control circuit is additionally required. Therefore, overall performance is not so good.
Also, in a conventional technology in which an external signal for controlling a slew rate is not used but in which a self control circuit is provided within an operational amplifier to improve a slew rate, a current is increased only in one of a differential input stage which receives input signals by P-channel FET's and a differential input stage which receives input signals by N-channel FET's. Therefore, a slew rate is limited by the threshold value Vt of transistors such as transistors MM5 and MM6, and the slew rate does not become high throughout wide input/output signal ranges.